Modeling Memory Errors in Pipelined Analog-to-digital Converters

Switched-capacitor implementations of pipelined ADCs contain several sources of memory errors, including capacitor dielectric absorption/relaxation, incomplete stage reset at high clock rates, and parasitic capacitance effects when op amps are shared between subsequent pipeline stages. This paper describes these sources of memory errors and presents a unified model for their effect. The dependence of these errors on circuit parameters and ADC sampling rate is also discussed. The effect of these errors on ADC linearity is then analyzed, showing how memory errors can limit the performance of a pipelined ADC.